ASIC Design House providing you solutions fromSpecifications to SiliconConvert an idea to specifications and SOWConvert the specs to RTL and test benchWrite the verification suite for the designDo Synthesis of the RTL to netlist at customer？s technology and generate test vectorsInsertion of JTAG, scan chain and ATPG generationLayout the netlist at the customer chosen technologyGenerate custom library, for simulation, synthesis and layoutCircuit and I/O design at up to 0.13 technologyFPGA to ASIC conversionMigration of old ASIC designs from obsolete processes to new technologiesPrograming in SKILL of Cadence plugin utilitiesWriting CAD/CAE SW for ASIC design activities.Writing scripts and automating tasks.